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?2001 integrated device technology, inc. november 2001 dsc 2674/11 1 idt7052s/l functional block diagram high-speed 2k x 8 fourport tm static ram features high-speed access ? commercial: 20/25/35ns (max.) ? industrial: 25ns (max.) ? military: 25/35ns (max.) low-power operation ? idt7052s active: 750mw (typ.) standby: 7.5mw (typ.) ? idt7052l active: 750mw (typ.) standby: 1.5mw (typ.) true fourport memory cells which allow simultaneous access of the same memory locations fully asynchronous operation from each of the four ports: p1, p2, p3, p4 versatile control for write-inhibit: separate busy input to control write-inhibit for each of the four ports memory array column i/o port 1 address decode logic port 2 address decode logic column i/o column i/o port 4 address decode logic port 3 address decode logic column i/o r/ w p1 i/o 0p1 -i/o 7p1 ce p1 oe p1 a 0p1 -a 10p1 busy p2 r/ w p2 ce p2 oe p2 2674 drw 01 i/o 0p2 -i/o 7p2 a 0p2 -a 10p2 busy p1 r/ w p4 i/o 0p4 -i/o 7p4 ce p4 oe p4 a 0p4 -a 10p4 busy p3 r/ w p3 ce p3 oe p3 i/o 0p3 -i/o 7p3 a 0p3 -a 10p3 busy p4 battery backup operation?2v data retention ttl-compatible; single 5v (10%) power supply available in 120 pin and 132 pin thin quad flatpacks and 108 pin pga military product compliant to mil-prf-38535 qml industrial temperature range (?40c to +85c) is available for selected speeds description the idt7052 is a high-speed 2k x 8 fourport? static ram designed to be used in systems where multiple access into a common ram is required. this fourport static ram offers increased system performance in multiprocessor systems that have a need to communicate in real time and also offers added benefit for high-speed systems in which multiple access is required in the same cycle. the idt7052 is also designed to be used in systems where on-chip
6.42 idt7052s/l high-speed 2k x 8 fourport? static ram military, industrial and commercial temperature ranges 2 notes: 1. all v cc pins must be connected to the power supply. 2. all gnd pins must be connected to the ground supply. 3. package body is approximately 1.21 in x 1.21 in x .16 in. 4. this package code is used to reference the package diagram. 5. this text does not indicate orientation of the actual part-marking. pin configurations (1,2,3) 2674 drw 02 oe p2 a 7 p2 a 8 p2 a 5 p2 80 i/o 2 p1 i/o 3 p1 i/o 6 p1 v cc gnd i/o 2 p4 i/o 5 p4 a 3 p2 a 4 p2 a 5 p3 a 7 p3 a 8 p3 oe p3 a 0 p2 a 1 p3 a 1 p2 a 0 p3 77 74 72 69 68 65 63 60 a 3 p3 a 4 p3 83 78 76 73 70 67 64 61 59 84 56 86 87 88 90 91 92 94 95 97 96 100 99 103 101 105 104 2 1 5 4 7 8 10 12 13 17 16 21 19 25 22 28 24 32 31 34 35 37 39 40 44 43 48 46 52 49 55 51 idt7052g g108-1 (4) 108-pin pga top view (5) abcdefghj kl m 81 57 54 53 82 79 75 71 66 62 58 50 r/ w p2 nc nc r/ w p3 busy p2 busy p3 a 6 p2 ce p3 a 2 p3 a 2 p2 a 6 p3 a 2 p4 a 1 p4 a 9 p3 a 9 p2 ce a 1 p1 a 2 p1 33 36 38 41 42 45 47 3 6 9 111415182023 29 30 26 27 85 89 93 98 102 106 107 108 nc p1 gnd a 5 p1 a 3 p1 a 0 p1 a 6 p1 a 4 p1 v cc ce p1 oe p1 i/o 0 p1 a 8 p1 a 9 p1 a 7 p1 r/ w p1 busy i/o 1 p1 v cc v cc v cc gnd i/o 6 p4 i/o 4 p1 i/o 7 p1 i/o 0 p2 i/o 2 p2 i/o 4 p2 i/o 6 p2 i/o 1 p3 i/o 3 p3 i/o 5 p3 i/o 7 p3 i/o 3 p4 i/o 4 p4 i/o 5 p1 nc i/o 1 p2 i/o 3 p2 i/o 5 p2 i/o 7 p2 i/o 0 p3 i/o 2 p3 i/o 4 p3 i/o 6 p3 i/o 0 p4 i/o 1 p4 a 0 p4 a 3 p4 a 5 p4 a 4 p4 a 6 p4 gnd p4 a 7 p4 a 8 p4 nc p4 a 9 p4 oe p4 r/ w gnd p4 i/o 7 p4 busy gnd ce 12 11 10 09 08 07 06 05 04 03 02 01 a 10 p1 a 10 p2 a 10 p3 a 10 p4 index 11/07/01 hardware port arbitration is not needed. this part lends itself to those systems which cannot tolerate wait states or are designed to be able to externally arbitrate or withstand contention when all ports simultaneously access the same fourport ram location. the idt7052 provides four independent ports with separate control, address, and i/o pins that permit independent, asynchronous access for reads or writes to any location in memory. it is the user?s responsibility to ensure data integrity when simultaneously accessing the same memory location from all ports. an automatic power down feature, controlled by ce , permits the on-chip circuitry of each port to enter a very low power standby power mode. fabricated using idt?s cmos high-performance technology, this fourport sram typically operates on only 750mw of power. low-power (l) versions offer battery backup data retention capability, with each port typically consuming 50w from a 2v battery. the idt7052 is packaged in a ceramic 108-pin pin grid array (pga), 120-pin thin quad flatpack (tqfp) and 132-pin plastic quad flatpack (pqf). military grade product is manufactured in compliance with the latest revision of mil-prf-38535 qml, making it ideally suited to military temperature applications demanding the highest level of performance and reliability.
6.42 idt7052s/l high-speed 2k x 8 fourport? static ram military, industrial and commercial temperature ranges 3 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 3 1 3 2 3 3 3 4 3 5 3 6 3 7 3 8 3 9 4 0 4 1 4 2 4 3 4 4 4 5 4 6 4 7 4 8 4 9 5 0 5 1 5 2 5 3 5 4 5 5 5 6 5 7 5 8 5 9 6 0 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 1 2 0 1 1 9 1 1 8 1 1 7 1 1 6 1 1 5 1 1 4 1 1 3 1 1 2 1 1 1 1 1 0 1 0 9 1 0 8 1 0 7 1 0 6 1 0 5 1 0 4 1 0 3 1 0 2 1 0 1 1 0 0 9 9 9 8 9 7 9 6 9 5 9 4 9 3 9 2 9 1 n/c n/c oe p2 busy p2 a 0p1 a 1p1 a 2p1 a 3p1 a 4p1 a 5p1 a 6p1 a 10p1 v cc a 7p1 a 8p1 a 9p1 n/c ce p1 r/ w p1 oe p1 busy p1 i/o 0p1 i/o 1p1 i/o 2p1 i/o 3p1 gnd i/o 4p1 i/o 5p1 n/c n/c n / c i / o 6 p 1 i / o 7 p 1 n / c v c c i / o 0 p 2 i / o 1 p 2 i / o 2 p 2 g n d i / o 3 p 2 i / o 4 p 2 i / o 5 p 2 v c c i / o 6 p 2 i / o 7 p 2 n / c i / o 0 p 3 i / o 1 p 3 v c c i / o 2 p 3 i / o 3 p 3 i / o 4 p 3 g n d i / o 5 p 3 i / o 6 p 3 i / o 7 p 3 v c c i / o 0 p 4 i / p 1 p 4 n / c n/c n/c busy p3 a 0p4 a 1p4 a 2p4 a 3p4 a 4p4 a 5p4 a 6p4 a 10p4 gnd a 7p4 a 8pr a 9p4 n/c ce p4 r/ w p4 oe p4 busy p4 gnd i/o 7p4 i/o 6p4 i/o 5p4 gnd i/o 4p4 i/o 3p4 i/o 2pr n/c n/c c e p 2 r / w p 2 n / c a 9 p 2 a 8 p 2 a 7 p 2 a 1 0 p 2 a 6 p 2 a 5 p 2 a 4 p 2 a 3 p 2 a 2 p 2 a 1 p 2 a 0 p 2 n / c a 0 p 3 a 1 p 3 a 2 p 3 a 3 p 3 a 4 p 3 a 5 p 3 a 6 p 3 a 1 0 p 3 a 7 p 3 a 8 p 3 a 9 p 3 n / c o e p 3 c e p 3 r / w p 3 2674 drw 04 idt7052pf pn120-1 (4) 120-pin thin quad flatpack top view (5) 11/07/01 pin configurations (1,2,3) (con't.) notes: 1. all v cc pins must be connected to the power supply. 2. all gnd pins must be connected to the ground supply. 3. pq132-1 package body is approximately .95 in x .95 in x .14 in. pn120-1 package body is approximately 14mm x 14mm x 1.4mm. 4. this package code is used to reference the package diagram. 5. this text does not indicate orientation of the actual part-marking 6. the side of the package containing pin1 may have a bevelled edge in place of the indicator dot.. idt7052pqf pq132-1 (4) 132-pin plastic quad flatpack top view (5,6) 1 17 117 116 18 50 51 83 84 n/c oe p2 busy p2 n/c a 0p1 a 1p1 a 2p1 a 3p1 a 4p1 a 5p1 a 6p1 a 7p1 a 8p1 a 9p1 n/c v cc n/c ce p1 r/ w p1 oe p1 busy p1 n/c i/o 0p1 i/o 1p1 i/o 2p1 i/o 3p1 i/o 4p1 i/o 5p1 n/c gnd n/c n/c i/o 2p4 i/o 3p4 i/o 4p4 i/o 5p4 i/o 6p4 i/o 7p4 n/c n/c gnd n/c gnd n/c ce p4 r/ w p4 oe p4 busy p4 n/c a 0p4 a 1p4 a 2p4 a 3p4 a 4p4 a 5p4 a 6p4 a 7p4 a 8p4 a 9p4 gnd n/c n/c busy p3 n/c 2674 drw 03 a 10p4 a 10p1 n / c a 9 p 2 a 8 p 2 a 7 p 2 a 6 p 2 a 5 p 2 a 4 p 2 a 3 p 2 a 2 p 2 a 1 p 2 a 0 p 2 n / c n / c n / c c e p 2 c e p 3 o e p 3 n / c n / c a 0 p 3 a 1 p 3 a 2 p 3 a 4 p 3 a 5 p 3 a 6 p 3 a 7 p 3 a 8 p 3 a 9 p 3 a 3 p 3 a 1 0 p 3 a 1 0 p 2 i / o 5 p 3 i / o 6 p 1 i / o 7 p 1 n / c v c c n / c i / o 0 p 2 i / o 1 p 2 i / o 2 p 2 i / o 3 p 2 i / o 4 p 2 i / o 5 p 2 g n d v c c i / o 0 p 3 i / o 1 p 3 i / o 2 p 3 i / o 3 p 3 i / o 4 p 3 i / o 6 p 3 i / o 7 p 3 i / o 0 p 4 i / o 1 p 4 n / c v c c g n d n / c n / c v c c n / c n / c i / o 7 p 2 r / w p 2 r / w p 3 i / o 6 p 2 11/07/01
6.42 idt7052s/l high-speed 2k x 8 fourport? static ram military, industrial and commercial temperature ranges 4 pin configurations (1,2) notes: 1. all v cc pins must be connected to the power supply. 2. all gnd pins must be connected to the ground supply absolute maximum ratings (1) notes: 1. stresses greater than those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. v term must not exceed vcc + 10% for more than 25% of the cycle time or 10ns maximum, and is limited to < 20ma for the period of v term > v cc + 10%. capacitance (1) (t a = +25c, f = 1.0mhz) tqfp only notes: 1. this parameter is determined by device characterization but is not production tested. 2. 3dv references the interpolated capacitance when the input and the output signals switch from 0v to 3v or from 3v to 0v. maximum operating temperature and supply voltage (1) recommended dc operating conditions notes: 1. v il > -1.5v for pulse width less than 10ns. 2. v term must not exceed vcc + 10%. notes: 1. this is the parameter t a . this is the "instant on" case temperature. symbol pin name a 0 p1 - a 10 p1 address lines - port 1 a 0 p2 - a 10 p2 address lines - port 2 a 0 p3 - a 10 p3 address lines - port 3 a 0 p4 - a 10 p4 address lines - port 4 i/o 0 p1 - i/o 7 p1 data i/o - port 1 i/o 0 p2 - i/o 7 p2 data i/o - port 2 i/o 0 p3 - i/o 7 p3 data i/o - port 3 i/o 0 p4 - i/o 7 p4 data i/o - port 4 r/w p1 read/wri te - port 1 r/w p2 read/wri te - port 2 r/w p3 read/wri te - port 3 r/w p4 read/wri te - port 4 gnd ground ce p1 chip enab le - port 1 ce p2 chip enab le - port 2 ce p3 chip enab le - port 3 ce p4 chip enab le - port 4 oe p1 output enab le - port 1 oe p2 output enab le - port 2 oe p3 output enab le - port 3 oe p4 output enab le - port 4 busy p1 write disable - port 1 busy p2 write disable - port 2 busy p3 write disable - port 3 busy p4 write disable - port 4 v cc power 2674 tbl 01 symbol rating commercial & industrial military unit v te r m (2 ) terminal voltage with re spect to gnd -0.5 to +7.0 -0.5 to +7.0 v t bias temperature unde r bias -55 to +125 -65 to +135 o c t stg storage temperature -65 to +150 -65 to +150 o c i out dc output current 50 50 ma 2674 tbl 02 grade ambient temperature gnd vcc military -55 o c to+125 o c0v5.0v + 10% commercial 0 o c to +70 o c0v5.0v + 10% industrial -40 o c to +85 o c0v5.0v + 10% 2674 tbl 04 symbol parameter conditions (2) max. unit c in input capacitance v in = 0v 9 pf c out output capacitance v out = 0v 10 pf 2674 tbl 03 symbol parameter min. typ. max. unit v cc supply voltage 4.5 5.0 5.5 v gnd ground 0 0 0 v v ih input high voltage 2.2 ____ 6.0 (2 ) v v il input low voltage -0.5 (1 ) ____ 0.8 v 2674 tbl 05
6.42 idt7052s/l high-speed 2k x 8 fourport? static ram military, industrial and commercial temperature ranges 5 notes: 1. 'x' in part number indicates power rating (s or l). 2. v cc = 5v, t a = +25c and are not production tested. 3. f = 0 means no address or control lines change. 4. at f = f max , address and control lines (except output enable) are cycling at the maximum frequency read cycle of 1/t rc , and using ?ac test conditions? of input levels of gnd to 3v. 5. for the case of one port, divide the appropriate current above by four. dc electrical characteristics over the operating temperature and supply voltage range (v cc = 5.0v 10%) n ote: 1. at vcc < 2.0v input leakages are undefined. dc electrical characteristics over the operating temperature and supply voltage range (1,5) (v cc = 5.0v 10%) symbol parameter condition 7052x20 com'l only 7052x25 com'l, ind & military 7052x35 com'l & military unit version typ. (2) max. typ. (2 ) max. typ. (2 ) max. i cc1 operating power supply current (all ports active) ce = v il outputs disabled f = 0 (3) com'l. s l 150 150 300 250 150 150 300 250 150 150 300 250 ma mil. & ind. s l ____ ____ ____ ____ 150 150 360 300 150 150 360 300 i cc2 dynamic operating current (all ports active) ce = v il outputs disabled f = f max (4) com'l. s l 240 210 370 325 225 195 350 305 210 180 335 290 ma mil. & ind. s l ____ ____ ____ ____ 225 195 400 340 210 180 395 330 i sb standby current (all ports - ttl leve l inputs) ce = v ih f = f max (4) com'l. s l 70 60 95 80 45 40 85 70 40 35 75 60 ma mil. & ind. s l ____ ____ ____ ____ 45 40 115 85 40 35 11 0 80 i sb1 full standby current (all po rts - all cmos level inputs) all ports ce > v cc - 0.2v v in > v cc - 0.2v or v in < 0. 2v, f = 0 (3) com'l. s l 1.5 0.3 15 1.5 1.5 0.3 15 1.5 1.5 0.3 15 1.5 ma mil. & ind. s l ____ ____ ____ ____ 1.5 0.3 30 4.5 1.5 0.3 30 4.5 2674 tbl 06 symbol parameter test conditions 7052s 7052l unit min. max. min. max. |i li | input leakage current (1 ) v cc = 5.5v, v in = 0v to v cc ___ 10 ___ 5a |i lo | output leakage current ce = v ih , v out = 0v to v cc ___ 10 ___ 5a v ol output low voltage i ol = 4ma ___ 0.4 ___ 0.4 v v oh output high voltage i oh = -4ma 2.4 ___ 2.4 ___ v 2674 tbl 07
6.42 idt7052s/l high-speed 2k x 8 fourport? static ram military, industrial and commercial temperature ranges 6 low v cc data retention waveform data retention characteristics over all temperature ranges (4) (l version only) v lc = 0.2v, v hc = v cc - 0.2v notes: 1. v cc = 2v, t a = +25c 2. t rc = read cycle time 3. this parameter is guaranteed but not production tested. 4. industrial temperature: for other speeds, packages and powers contact your sales office. ac test conditions figure 1. ac output test load figure 2. output test load (for t lz , t hz , t wz , t ow ) *including scope and jig symbol parameter test condition min. typ. (1) max. unit v dr v cc fo r data rete ntion v cc = 2 v 2.0 ___ ___ v i ccdr data retention current ce > v hc v in > v hc or < v lc com'l. ___ 25 600 a mil. & ind. ___ 25 1800 t cdr (3 ) chip dese lect to data retentio n time 0 ___ ___ ns t r (3 ) operation recovery time t rc (2 ) ___ ___ ns 2674 tbl 08a data retention mode v cc ce 2674 drw 05 4.5v t cdr t r v ih v dr v ih 4.5v v dr 2v 347 ? 893 ? 30pf 5v 2674 drw 06 data out 347 ? 893 ? 5pf* 5v data out , input pulse levels input rise/fall times input timing reference levels output reference levels output load gnd to 3.0v 5ns max. 1.5v 1.5v fi gures 1 and 2 2674 tbl 08b
6.42 idt7052s/l high-speed 2k x 8 fourport? static ram military, industrial and commercial temperature ranges 7 2674 drw 08 t aoe t lz t hz data out ce t ace valid data oe current i cc i sb t pu 50% t lz t pd 50% t hz 2674 drw 07 t aa t oh t oh data out address t rc data valid previous data valid timing waveform of read cycle no. 1, any port (1) ac electrical characteristics over the operating temperature and supply voltage (3) notes: 1. transition is measured 0mv from low or high-impedance voltage with the output test load (figure 2) 2. this parameter is guaranteed by device characterization but is not production tested. 3. 'x' in part number indicates power rating (s or l) timing waveform of read cycle no. 2, any port (1,2) notes: 1. r/ w = v ih , oe = v il and ce = v il. notes: 1. r/ w = v ih for read cycles. 2. addresses valid prior to or coincident with ce transition low. 7052x20 com'l only 7052x25 com'l, ind & military 7052x35 com'l & military symbol parameter min.max.min.max.min.max.unit read cycle t rc re ad cycle time 20 ____ 25 ____ 35 ____ ns t aa address access time ____ 20 ____ 25 ____ 35 ns t ace chip enable access time ____ 20 ____ 25 ____ 35 ns t aoe output enable access time ____ 10 ____ 15 ____ 25 ns t oh output hold from address change 0 ____ 0 ____ 0 ____ ns t lz output low-z time (1,2) 5 ____ 5 ____ 5 ____ ns t hz output high-z time (1,2) ____ 12 ____ 15 . ____ 15 ns t pu chip enable to power up time (2 ) 0 ____ 0 ____ 0 ____ ns t pd chip disable to power down time (2) ____ 20 ____ 25 ____ 35 ns 2674 tb l 0 9
6.42 idt7052s/l high-speed 2k x 8 fourport? static ram military, industrial and commercial temperature ranges 8 ac electrical characteristics over the operating temperature and supply voltage (7) notes: 1. transition is measured 0mv from low or high-impedance voltage with the output test load (figure 2). 2. this parameter is guaranteed by device characterization but is not production tested. 3. if oe = v il during a r/ w controlled write cycle, the write pulse width must be the larger of t wp or (t wz + t dw ) to allow the i/o drivers to turn off data to be placed on the bus for the required t dw . if oe = v ih during an r/w controlled write cycle, this requirement does not apply and the write pulse can be as short as the specified t wp . specified for oe = v ih (refer to ?timing waveform of write cycle?, note 8). 4. port-to-port delay through ram cells from writing port to reading port, refer to ?timing waveform of write with port-to-port read?. 5. to ensure that the write cycle is inhibited on port "a" during contention from port "b". port "a" may be any of the four port s and port "b" is any other port. 6. to ensure that a write cycle is completed on port "a" after contention from port "b". port "a" may be any of the four ports a nd port "b" is any other port. 7. 'x' in part number indicates power rating. 7052x20 com'l only 7052x25 com'l & military 7052x35 com'l & military symbol parameter min.max.min.max.min.max.unit wri t e cycl e t wc write cycle time 20 ____ 25 ____ 35 ____ ns t ew chip enable to end-of-write (3) 15 ____ 20 ____ 30 ____ ns t aw address valid to end-of-write 15 ____ 20 ____ 30 ____ ns t as address set-up time 0 ____ 0 ____ 0 ____ ns t wp write pulse width (3) 15 ____ 20 ____ 30 ____ ns t wr write recovery time 0 ____ 0 ____ 0 ____ ns t dw data valid to end-of-write 15 ____ 15 ____ 20 ____ ns t hz output high-z time (1,2) ____ 15 ____ 15 ____ 15 ns t dh data ho ld time 0 ____ 0 ____ 0 ____ ns t wz write enable to output in high-z (1,2) ____ 12 ____ 15 ____ 15 ns t ow outp ut active fro m end-of-write (1,2) 0 ____ 0 ____ 0 ____ ns t wdd write pulse to data delay (4 ) ____ 35 ____ 45 ____ 55 ns t wdd write data valid to read data delay (4 ) ____ 30 ____ 35 ____ 45 ns busy input timing t wb write to busy (5) 0 ____ 0 ____ 0 ____ ns t wh write hold after busy (6) 15 ____ 15 ____ 20 ____ ns 2674 tbl 10
6.42 idt7052s/l high-speed 2k x 8 fourport? static ram military, industrial and commercial temperature ranges 9 timing waveform of write cycle no. 1, r/ w controlled timing (5,8) timing waveform of write cycle no. 2, ce controlled timing (1, 5) notes: 1. r/ w or ce = v ih during all address transitions. 2. a write occurs during the overlap (t ew or t wp ) of a ce = v il and a r/ w = v il . 3. t wr is measured from the earlier of ce or r/ w = v ih to the end of write cycle. 4. during this period, the i/o pins are in the output state, and input signals must not be applied. 5. if the ce = v il transition occurs simultaneously with or after the r/ w = v il transition, the outputs remain in the high-impedance state. 6. timing depends on which enable signal is asserted last, ce or r/ w . 7. transition is measured 0mv from low or high-impedance voltage with the output test load (figure 2). this parameter is guarant eed but is not production tested. 8. if oe = v il during a r/ w controlled write cycle, the write pulse width must be the larger of t wp or (t wz + t dw ) to allow the i/o drivers to turn off data to be placed on the bus for the required t dw . if oe = v ih during an r/ w controlled write cycle, this requirement does not apply and the write pulse can be as short as the specified t wp . ce 2674 drw 09 t aw t as t wr t dw data in address t wc r/ w t wp data out t wz (7) (4) (4) (2) t ow oe t hz t lz (7) t hz (6) (3) (9) t dh (7) ce 2674 drw 10 t aw t as t wr t dw data in address t wc r/ w t ew t dh (9) (6) (2) (3)
6.42 idt7052s/l high-speed 2k x 8 fourport? static ram military, industrial and commercial temperature ranges 10 timing waveform of write with port-to-port read (1,2,3) functional description the idt7052 provides four ports with separate control, address, and i/o pins that permit independent access for reads or writes to any location in memory. these devices have an automatic power down feature controlled by ce . the ce controls on-chip power down circuitry that permits the respective port to go into standby mode when not selected ( ce = v ih ). when a port is enabled, access to the entire memory array is permitted. each port has its own output enable control ( oe ). in the read mode, the port?s oe turns on the output drivers when set low. read/ write conditions are illustrated in the table below. timing waveform of write with busy input notes: 1. busy is asserted on port "b" blocking r/ w "b" until busy "b" goes high. truth table i ? read/write control (3) notes: 1. "h" = v ih , "l" = v il , "x" = don?t care, "z "= high impedance 2. if busy = v il , write is blocked. 3. for valid write operation, no more than one port can write to the same address location at the same time. notes: 1. assume busy input = v ih and ce = v il for the writing port. 2. oe = v il for the reading ports. 3. all timing is the same for left and right ports. port "a" may be either of the four ports and port "b" is any other port. 2674 drw 11 addr "a" t wc data "b" match t wp r/ w "a" data in"a" addr "b" t dh valid match valid t ddd t wdd t dw 2674 drw 12 r/ w "a" busy "b" t wp t wh t wb r/ w "b" (1) , any port (1) r/ w ce oe d 0-7 function x h x z port deselected: power-down xhx z ce p1 = ce p2 = ce p3 = ce p4 =v ih power down mode i sb or i sb1 llx data in data on port written into memory (2) hlldata out data in memory output on port x x h z outputs disabled 2674 tbl 1 1
6.42 idt7052s/l high-speed 2k x 8 fourport? static ram military, industrial and commercial temperature ranges 11 ordering information note: 1. industrial temperature range is available. for specific speeds, packages and powers contact your sales office. a power 999 speed a package a process/ temperature range blank i (1) b commercial (0c to +70c) industrial (-40c to +85c military (-55c to +125c) compliant to mil-prf-38535 qml g pqf pf 108-pin pin grid array (g108-1) 132-pin plastic quad flatpack (pq132-1) 120-pin thin quad plastic flatpack (pn120-1) 20 25 35 xxxx device type idt speed in nanosecond s 2674 drw 13 l s low power standard power 7052 16k (2k x 8) fourport ram commercial only commercial, industrial & military commercial & military , the idt logo is a registered trademark of integrated device technology, inc. datasheet document history 1/18/99: initiated datasheet document history converted to new format cosmetic typographical corrections added additional notes to pin configurations 6/4/99: changed drawing format page1 corrected dsc number 11/10/99: replaced idt logo 11/18/99: page 10 fixed typo in caption for busy input waveform 5/23/00: page 4 increased storage temperature parameter clarified t a parameter page 5 dc electrical parameters?changed wording from "open" to "disabled" changed 200mv to 0mv in notes corporate headquarters for sales: for tech support: 6024 silver creek valley road 800-345-7015 or 408-284-8200 408-284-2794 san jose, ca 95138 fax: 408-284-2775 dualporthelp@idt.com www.idt.com 10/22/01: pages 2 & 3 added date revision for pin configurations page 5, 7 & 8 added industrial temp to column heading for 25ns speed to dc & ac electrical characteristics page 11 added industrial temp offering to 25ns ordering information page 4, 5, 7 & 8 removed industrial temp footnote from all tables page 1 & 11 replace tm logo with ? logo

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